1. Field of the Invention
This invention relates to integrated circuits and more particularly to capacitors in memory devices.
2. Description of Related Art
U.S. Pat. No. 5,116,776 of Chan et al "Method of Making a Stacked Capacitor for DRAM Cell" describes a storage node composed of multiple layers of polysilicon sandwiched between two polysilicon ground plate layers.
U.S. Pat. No. 5,155,056 of Jeong-Gyoo "Process for Formation of Cells having Self-Aligned Capacitor Contacts, and Structure Therefor" describes a method of making a stacked capacitor from polysilicon. The stack polysilicon is patterned using photoresist and an ion implantation is performed using the stack polysilicon as a mask.
In Fazan et al "Reliability and Characterization of Composite Oxide/Nitride Dielectrics for Multi-Megabit Dynamic Random Access Memory Stacked Capacitors", J. Electrochem. Soc., Vol. 138, No. 7, 2052-2056 (July 1991) describes at page 2053 in FIG. 1 stacked DRAM cell. The disadvantages are firstly that the bit line contact step coverage is a problem and the aspect ratio is very high. It is even a greater problem for increasing the storage node height to increase capacitance. Secondly, the capacitor area is limited by bit line contact to cell plate alignment limitations. Thus, a buried bit line approach is desirable to solve such problems.
Kimura et al "A New Stacked Capacitor DRAM Cell Characterized by a Storage Capacitor on a Bit-line Structure" IEDM 596-599 (1988) describes a Diagonal Active Stacked cell with a Highly-packed storage node (DASH) device in FIG. 2 thereof on page 597. The disadvantages of the DASH cell are the diagonal active area and word line layout. The device is more sensitive to polysilicon to active alignment. Secondly, the node contact to bit line has alignment limitations or must use the complicated Self-Aligned Contact (SAC) technique.
Sakao et al "A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64 Mb DRAMs" IEDM 90-655 to 90-658 (1990) shows on page 657 in FIG. 1 thereof an illustration of the bit and word lines interconnection. A first layer polysilicon 1 word line is vertical to the third layer polysilicon 3 bit line. The interconnection line is composed of polysilicon 2. Disadvantages of the COB cell are first that one needs an extra local interconnection layer for the node extension and secondly, as above, that the node contact to the bit lines also have alignment limitations or must use the complicated Self-Aligned Contact (SAC) technique.
An object of this invention is to use a rectangular active area which is not sensitive to polysilicon alignment.
Another object of this invention is connecting a storage node directly through a bit line so there are no alignment issues or need for complicated Self Aligned Contact (SAC) techniques.
A third object of this invention is to retain all the advantages of a buried bit line DRAM cell.
Still another object of this invention is to connect the storage plate directly through a polysilicon bit line to contact the N+ node to prevent an extra local interconnect layer thereby simplifying the process and the topology.